There are a number of situations that can cause a memory array or logic circuitry to display "fails" which are detected by a BIST (Built In Self Tester), or other kinds of logic and memory tests. Early user hardware and circuit characterization are two typical examples of where circuits can exhibit fails that are to be further investigated. These fails can occur because of mask defects, logic or memory design errors, logic or memory test errors, or the like. In each of these cases, characterization of the parts of the memory array or logic circuits that did not fail is essential. However, characterization of the portions of the memory array or logic circuitry that did not fail is not within the designed capability of BIST. BIST does not allow disabling of known fails.
While testing a memory array or logic circuit with BIST, a single understood fail will cause the fail flag to become active and thus potentially mask other fails in the circuit. This means that after each cycle the test must be stopped and the data in each of the output latches examined to determine if the fail flag is masking other fails in the memory array or logic circuitry. Thus the circuit characterization test becomes much more labor intensive, and a complete test can not easily be performed because of the required cycle by cycle analysis.